Field of Invention
The present invention is related to an integrated circuit and a method of forming the same, and more generally to a semiconductor device and a method of forming the same.
Description of Related Art
As technology advances, memory devices are minimized to meet the trend of lighter, thinner, shorter and smaller products. As the size of a memory device is scaled down, the distance between adjacent gates becomes shorter and the spacer width becomes smaller, resulting in a high inter-gate capacitive coupling and even a leakage current. Therefore, the performance of the device is degraded.
Besides, with the development of a multi-functional chip, integrating elements with different functions, e.g., a memory and a metal-oxide-semiconductor (MOS) transistor, into the same chip has become the mainstream in the market. However, the process for fabricating a memory is commonly separated from the process for fabricating a MOS transistor. Hence, multiple photo-masks and complicated process steps are required, so as to increase the process cost and weaken the competitiveness. Therefore, how to effectively integrate a memory and a MOS transistor has been drawn high attention in the industry.